Transactional Memory and Lock Elision

I started reading a post on recent trends in hardware and their implications on distributed systems design. One of the recent additions that could make parallel programming much easier is the TSX extensions in Intel Haswell processors.

 

It comes in two flavors, a backwards-compatible Hardware Lock Elision (HLE) instruction set, and a more flexible forward-looking Restricted Transactional Memory (RTM) instruction set. Here are a few blog posts and papers that give a good overview of Intel TSX and it’s origins in academia.

 

Brief introduction into Intel TSX and it’s implications for the industry

http://www.anandtech.com/show/6290/making-sense-of-intel-haswell-transactional-synchronization-extensions

Analysis of Haswell’s transactional memory by David Kanter

http://www.realworldtech.com/haswell-tm/1/

Hardware Lock Elision on Haswell

https://brooker.co.za/blog/2013/12/14/intel-hle.html

Lock elision support in gcc and linux

http://halobates.de/adding-lock-elision-to-linux.pdf

The original paper on Speculative Lock Elision: Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution

http://pages.cs.wisc.edu/~rajwar/papers/micro01.pdf

 

 

 

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